Chamfer is to grind away the sharp edges and corners around the wafer. Its purpose is to make the mechanical strength of the wafer bigger prevent the wafer edge from cracking, to prevent damage caused by thermal stress, and to increase the flatness of [...]
2022-06-10meta-author
PAM XIAMEN offers Indium Foil.
Indium ( In ) Foil: 100 mm (W) x 100 mm ( L) x 0.1 mm ( T)
Polycrystal In Foil
Purity: > 99.995%
Size: 0.10 mm thickness x 100mm width x 100 mm Length
Surface finish: as cold rolling [...]
2019-05-08meta-author
Annealed silicon wafer can be provided with low defect density from PAM-XIAMEN. The purpose of using annealed wafer is to eliminate defects on the silicon wafer surface and the component manufacturing area of the surface layer, and has a strong ability to capture heavy [...]
2019-02-26meta-author
We provide thermal oxide wafer with/without Ti layer/Pt layer in diameter from 2″ to 6″,now we give examples as follows:
1) 4 inch,silicon prime/test wafer,deposited with 5000 Angstroms of silicon oxide
2) Pt layer+Ti layer+thermal oxide layer deposit on silicon wafer:
4 inch Prime grade silicon,1-20 ohm [...]
Compared to 4H-SiC, although the bandgap of 3C silicon carbide (3C SiC) is lower, its carrier mobility, thermal conductivity, and mechanical properties are better than those of 4H-SiC. Moreover, the defect density at the interface between the insulating oxide gate and 3C-SiC is lower, which is [...]
2023-12-08meta-author
PAM XIAMEN offers test grade silicon wafers
Below is just a short list of the test grade silicon substrates!
Inches
Cust class
Dopant
Type
Orientation
PFL length
PFL direction
SFL
Off orientation
Resistivity
Diameter
Thickness
Bow
TTV
Warp
6
SSP
Red Phos.
N+
100
47,5 ± 2,5
01T ± 0,50
0.0 ± 0.5°
0.015 – 0.035 Ohmcm
150 ± 0.5 mm
400 ± 15 µm
40
5
40
6
SSP
Red Phos.
N+
100
47,5 ± 2,5
01T ± 0,50
0.0 ± 0.5°
0.015 [...]
2019-02-25meta-author